As application specific integrated circuit (ASIC) process nodes advance, and device currents continue to scale in support of ever higher very large scale integration (VLSI) gate counts, delivering, or ensuring the delivery of, the requisite power to ASICs is becoming a significant challenge. In particular, noise specifications are becoming increasingly difficult to satisfy. As an example, the power delivery must account for voltage droops (e.g., the intentional loss in output voltage from a device as it drives a load) driven by current consumption, while voltage droop budgets (e.g., the amount of voltage droop that can be accommodated without negatively impacting power delivery) are decreasing with decreases in operating voltages of ASICs. Moreover, current consumption only increases as the device count increases, thereby increasing the difficulty of delivering the requisite power (e.g., clean power) to ASIC devices. More specifically, reduced operating voltage linearly reduces allowable voltage droop while increasing current demand linearly increases actual voltage droop. Consequently, an alternate approach to power distribution is needed.